 Transistor Biasing - Engineer Simple

# Transistor biasing-It has formerly been bandied that for faithful modification, a transistor amplifier must satisfy three introductory conditions,

## Videlicet

(i) proper zero signal collector current,

(ii) proper
base-emitter voltage at any moment and

(iii) proper collector-emitter voltage at any
moment.

It's the fulfillment of these conditions which is know as transistor turning.
The proper inflow of zero signal collector current and the conservation of proper
collector-emitter voltage during the passage of signal is know as transistor turning.

The introductory purpose of transistor biasing is to keep the base-emitter junction
duly forward prejudiced and collector- base junction duly rear poisoned during the
operation of signal.

This can be achieve with a bias battery or associating a circuit with a transistor.

The ultimate system ids more effective and is constantly retainer.

The circuit which provides transistor biasing is know as turning circuit. It may be note that
transistor biasing is veritably essential for the proper operation of transistor in any circuit.

### Example 1. An npn silicon transistor has V CC = .6 V and the collector load R C =2.5 k Find:

( i) The maximum collector current that can be allow during the operation
of signal for faithful modification.

(ii) The maximum zero signal collector current needed result. Collector force voltage, V CC = 6 V
Collector load, R C = 2.5 k

(i) We know that for faithful amplification, V CE shouldn't be lower than 1 V for
silicon transistor.

Max. Voltage allowed across RC = 6 1 = 5 V

Max. Allowed collector current = 5 V/ R C = 5 V/2.5 k = 2mA

### Thus, the maximum collector current allowed during any part of the signal is 2mA. If the collector current is allowed to rise above this value, V CE will fall below 1 V.

consequently, value of will fall, resulting in unfaithful amplification.

(ii) During the negative peak of the signal, collector current can at the most be
allowed to become zero. As the negative and positive half cycles of the signal are
equal,therefore, the changes in collector current due to these will also be equal but in
opposite direction.
Minimum zero signal collector current required = 2 mA/2 = 1mA
During the positive peak of the signal

[point A in Fig. 1 (ii)], i C = 1+1 = 2mA
and during the negative peak (point B),
i C = 1 - 1 = 0 mA

### Example-2. A transistor employs a 4 k load and V CC = 13V. what is themaximum input signal if = 100 ? 1V and a change of 1V in V BE causes a change of 5mAin collector current.

#### Solution:

Collector supply voltage, V CC = 13 V
Knee voltage, V knee = 1 V
Collector load, R C = 4 k
Max. allowed voltage across, R C = 13-1 = 12 V